Design Verification Engineer

Overview

Develop and verify hardware designs using UVM, SystemVerilog, C/C++ and related tools.

Key Responsibilities

• verification
• assertion
• coverage
• debugging

Tasks

-Perform constraint random verification, assertion writing, coverage analysis, debugging.

Requirements

• uvm
• systemverilog
• arm
• c/c++
• fpga
• eda

What You Bring

-Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus. -Work with ARM cores, formal verification, SV DPI-C. -Strong understanding of semiconductor design and verification methodologies -Work on HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows. -Experience with verification tools such as UVM, System Verilog, and Verilog -Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.

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About Quest Global

-By blending deep technical know‑how with digital innovation, it evolved into a global engineering partner. -Projects range from next‑gen automotive safety systems and AI‑driven semiconductors to cutting‑edge aerospace and defense platforms. -Its financial growth is steady—built on recurring partnerships with Fortune‑top‑10 clients across key sectors. -A hallmark project: sustaining global EMS/ADMS energy‑management software for a major utilities provider. -Another standout: accelerating MRI development and support globally for a leading MedTech firm. -Its edge lies in full‑lifecycle delivery—concept, design, embedded software, manufacturing support, digital sustenance. -Known for foresight, the firm not only solves challenges but anticipates and prevents them.

Sector Specialisms