Principal Engineer, ASIC Development Engineering (RTL Design)

Overview

Design and implement ASIC IPs/subsystems, lead a small team, and handle debugging/verification.

Requirements

• verilog
• uvm
• pcie
• eda
• 10+ years
• leadership

What You Bring

-Experience in grooming team of 1-4 engineers, interacting with many team -Strong digital design development and execution skills , solving bugs -Deep expirience in debug , solving problem, see the architecture view, proposing solutions. -At hands on in IP / blocks / subsystem complex design in verilog / sysverilog -Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly -BE or Master's in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field -Deep knowledge on PCIe, axi , DMA, AHB interfaces -Experience in Verification UVM , DDR , flash is a plus -10+ years of experience in ASIC development, with a proven track record of leading complex projects -8+ years of experience in ASIC development, with a proven track record of leading complex project -Understanding of semiconductor industry trends and willingness to work in Bengaluru, India, with occasional travel -Expertise in high-performance and low-power design techniques -Expertise in high-performance and low-power design techniques, with hands-on experience using industry-standard EDA tools -Hands-on experience with industry-standard EDA tools and design flows -BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field -Advanced knowledge of ASIC design and development, including digital design, verification methodologies, and proficiency in hardware description languages (e.g., Verilog, VHDL) -Strong problem-solving, debugging, and analytical skills to resolve complex technical issues -Excellent leadership, mentoring, and communication skills, with the ability to guide engineering teams and articulate complex technical concepts

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