Lead Engineer - Physical Design

About the Role

• Ownership of block flow from RTL/Netlist to GDSII, including CTS, custom clocking, and routing to sign‑off. • Drive design quality improvements and optimize area, power, and performance through flow tuning.

Key Responsibilities

• ▸rtl flow
• ▸gdsii
• ▸cts
• ▸routing
• ▸design quality
• ▸performance

What You Bring

The role requires deep, hands‑on expertise in synthesis, place‑and‑route, clock‑tree synthesis, timing analysis and physical verification for sub‑3nm technologies. Candidates must be proficient with Cadence Innovus, power‑efficiency techniques, IR‑drop and EM fixes, and have working knowledge of Redhawk, ICV, PrimeTime, Formality and Fusion Compiler. Ownership of the block flow—from RTL and netlist through GDSII, including CTS, custom clocking and routing to sign‑off—is expected, along with the ability to write timing ECOs and apply ECO methodologies. Experience leading small teams of three to five engineers and strong scripting skills in Tcl or Perl, plus familiarity with YAML, are advantageous. • Hands‑on knowledge of synthesis, place‑and‑route, CTS, timing analysis/STA, and physical verification for ≤3nm technologies. • Proven expertise in synthesis, design constraints, floorplan (macro placement), timing concepts, and block‑level formal verification. • Experience with Cadence Innovus flow; familiarity with power‑efficiency techniques, IR‑drop, EM fixes; Redhawk knowledge is a plus. • Proficiency with ICV, PrimeTime, Formality, and Fusion Compiler tools. • Ability to write timing ECOs and apply ECO methodologies. • Experience leading small teams (3‑5 engineers) is a plus. • Good scripting skills in Tcl or Perl; understanding of YAML files is a plus.

Requirements

• ▸synthesis
• ▸place‑and‑route
• ▸cadence innovus
• ▸primetime
• ▸tcl/perl
• ▸team‑lead

Work Environment

Office Full-Time