AMS Verification engineer

About the Role

Documentation and post‑silicon support are also part of the role. You will create clear verification plans, maintain results documentation, and assist with post‑silicon validation and debug to reproduce and resolve hardware issues. • Develop detailed AMS verification plans and create test benches for block‑level and top‑level designs. • Build accurate behavioral models using Verilog‑AMS, SystemVerilog RNM, or wreal. • Perform mixed‑signal simulations with tools like Cadence Virtuoso, Spectre, Xcelium, or Synopsys VCS‑AMS and debug analog‑digital interactions. • Drive improvement of verification methodologies and implement techniques to boost coverage and efficiency. • Collaborate with analog designers, digital designers, and firmware teams to address verification concerns. • Automate test flows, manage regressions, and analyze results using Python, Perl, or TCL scripts. • Document verification plans, environments, and outcomes clearly and concisely. • Provide post‑silicon validation support and debug hardware issues.

Key Responsibilities

• ▸verification plans
• ▸behavioral modeling
• ▸mixed‑signal sim
• ▸methodology improvement
• ▸test automation
• ▸post‑silicon validation

What You Bring

We are seeking a highly motivated and skilled Analog/Mixed-Signal (AMS) Verification Engineer to join our team. In this role, you will be responsible for ensuring the quality, functionality, and performance of our complex mixed-signal semiconductor products. You will work closely with analog and digital design teams to develop and execute comprehensive verification plans, ensuring our chips are robust and bug‑free before they go to tape‑out. This is a critical position that requires a strong blend of analog circuit knowledge, digital verification methodologies, and a passion for problem‑solving. Candidates must hold a Bachelor’s or Master’s degree in Electrical or Computer Engineering and have several years of hands‑on AMS verification experience. A solid understanding of analog circuit design, expertise in Verilog‑AMS or SystemVerilog RNM, familiarity with mixed‑signal simulation tools, and proficiency in digital verification methodologies such as UVM are required. Strong scripting, problem‑solving, and teamwork skills are essential. • Hold a Bachelor’s or Master’s degree in Electrical, Computer Engineering, or a related field. • Possess several years of hands‑on AMS verification experience. • Understand analog circuit concepts such as PLLs, ADCs, DACs, amplifiers, and SERDES. • Expert in Verilog‑AMS and/or SystemVerilog RNM. • Proficient with at least one mixed‑signal simulation tool (e.g., Cadence Xcelium, Mentor Symphony, Synopsys VCS‑AMS). • Experienced with digital verification methodologies, including UVM. • Skilled in scripting languages (Python, Perl, TCL) for automation. • Able to read and interpret analog schematics and digital RTL. • Demonstrate strong problem‑solving, analytical, debugging, communication, and teamwork abilities. • Experience with Cadence Virtuoso for schematic capture and analog simulation. • Familiarity with formal verification, linting, or CDC tools. • Domain experience in automotive, high‑speed interfaces (PCIe, USB, Ethernet), or power management. • Knowledge of Verilog‑A for analog behavioral modeling.

Requirements

• ▸bachelors degree
• ▸ams verification
• ▸verilog‑ams
• ▸mixed‑signal sim
• ▸uvm
• ▸python

Work Environment

Hybrid