Lead Engineer - AMSDV

About the Role

• Use mixed‑signal verification environments and regression tools (Cadence Virtuoso, Spectre, xCelium, Incisive, vManager, IMC). • Read analog schematics and extract main functionality. • Write Verilog‑based RTL code and follow ASIC design methodology. • Apply SystemVerilog advanced verification techniques: assertions, constrained randomization, metric‑driven verification, and UVM. • Create behavioral models of analog blocks using SystemVerilog (RNM) and Verilog‑AMS. • Model analog and mixed‑signal blocks for simulation and verification. • Develop basic scripts in UNIX shell, Perl, Python, or TCL as needed.

Key Responsibilities

• ▸mixed‑signal verification
• ▸analog schematics
• ▸rtl coding
• ▸systemverilog verification
• ▸behavioral modeling
• ▸script development

What You Bring

We are hiring for two Analog Mixed‑Signal Design Verification (AMS DV) engineer positions in Bangalore. The ideal candidate has 4‑6 years of relevant experience and will work on ASIC verification projects. The role involves using mixed‑signal verification environments and regression tools such as Cadence Virtuoso, Spectre, xCelium, Incisive, vManager and IMC. Candidates must be able to read analog schematics, write Verilog‑based RTL, and apply SystemVerilog methodologies including assertions, constrained randomization, metric‑driven verification, and UVM. Familiarity with behavioral modeling of analog blocks using SystemVerilog (RNM) and Verilog‑AMS, as well as basic UNIX, Perl, Python and TCL scripting, is also required. • Demonstrate strong fundamentals in analog and mixed‑signal circuit concepts and topologies.

Requirements

• ▸analog mixed‑signal
• ▸asic verification
• ▸cadence virtuoso
• ▸systemverilog
• ▸uvm
• ▸python

Work Environment

Office Full-Time