Quest Global
Solving the world’s hardest engineering challenges through end‑to‑end solutions across industries.
DFT Engineer
Define and implement DFT specs, flow automation, and integration across teams.
Job Highlights
About the Role
• Define and review DFT specifications, covering test strategy, coverage goals, scan architecture, compression, boundary scan, MBIST/repair, and SSN methodology. • Architect and implement hierarchical DFT methodology from block to top‑level to enable scalable ATPG and pattern delivery. • Develop and maintain automation strategies for DFT flow using Python/TCL, enhancing internal methodology. • Collaborate with RTL, STA, PD, verification, and ATE/validation teams for seamless DFT integration and pattern rollout. • Ensure sign‑off of DFT timing constraints, I/O and clock constraints, and support STA/debug teams for timing closure. • Perform verification using VCS/VSIM RTL and GLS simulations, fault simulation, and coverage analysis. • Create DFT SDC constraints for scan shift, capture, at‑speed, MBIST, and understand timing exceptions.
Key Responsibilities
- ▸dft specification
- ▸hierarchical dft
- ▸automation scripts
- ▸timing signoff
- ▸verification simulation
- ▸sdc constraints
What You Bring
• Proficient with Siemens Tessent (Scan, SSN, MBIST, BISTArchitect, iJTAG, Repair, VCS) and Synopsys SpyGlass DFT/TestMAX tools. • Experienced in IEEE 1149.1/1500, iJTAG, and 1687 standards. • Skilled in DFT techniques: Scan, Compression, Boundary Scan, ATPG, SSN, iJTAG, MBIST, Redundancy Repair, and Memory BIST architectures. • Strong scripting expertise in Python, TCL, and Perl for flow and regression automation. • Experience developing or supporting DFT flow scripts and regression automation. • Exposure to hierarchical DFT pattern generation and reuse at SoC level. • Knowledge of low‑power DFT challenges and power‑aware ATPG.
Requirements
- ▸tessent
- ▸spyglass
- ▸ieee1149
- ▸python
- ▸hierarchical dft
- ▸low‑power dft
Work Environment
Onsite