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Validation Engineer (Medical Industry)
Bepc Inc. - Business Excellence Professional ConsultingValidate medical device equipment and processes to ensure regulatory compliance
Santa Clara, CA
9 days ago
Onsite
sop development
iq/oq validation
pq validation
six sigma
gd&t
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Validate equipment, fixtures, and processes for medical device/pharma compliance.
Santa Clara, CA
9 days ago
Office Full-Time
validation docs
protocol execution
project management
iso 13485
six sigma
PEOPLE ALSO SEARCHED FOR:
Validate medical device equipment, fixtures, and labs ensuring compliance with FDA/ISO standards.
Santa Clara, CA
9 days ago
Onsite
troubleshooting
compliance
validation lifecycle
validation
iso 13485
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Validation Engineer I (Medical Industry)
Bepc Inc. - Business Excellence Professional ConsultingValidate equipment, fixtures, and lab systems to ensure FDA/ISO compliance.
Santa Clara, CA
9 days ago
Onsite
validation lifecycle
iq/oq execution
root cause
english
iq/oq
PEOPLE ALSO SEARCHED FOR:
Validate equipment and fixtures per FDA/ISO standards for medical device manufacturing.
San Jose, CA
9 days ago
Office Full-Time
validation lifecycle
iq/oq protocols
regulatory compliance
iso 13485
fda 820
PEOPLE ALSO SEARCHED FOR:
Perform IQ/OQ/PQ validation, create protocols/reports, and ensure GMP compliance for medical devices.
Santa Clara, CA
9 days ago
Office Full-Time
validation docs
pq execution
iq/oq protocols
iso 13485
six sigma
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Design Verification Engineer
Quest GlobalPerform HVL/SystemVerilog verification, coding, debugging, and coverage analysis.
San Jose, CA
10 days ago
Office Full-Time
random verification
assertion writing
coverage analysis
uvm
systemverilog
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Sr. Display Validation Engineer
Quest GlobalValidate and test wearable display systems and optical components for new products.
Sunnyvale, CA
10 days ago
Office Full-Time
display validation
test plans
hands‑on testing
master's ee
python
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Design Verification Engineer
Quest GlobalPerform verification using UVM/SystemVerilog and related tools.
San Jose, CA
10 days ago
Office Full-Time
random verification
assertion writing
coverage analysis
uvm
systemverilog
PEOPLE ALSO SEARCHED FOR:
Senior Design Verification Engineer
Quest GlobalDevelop and lead verification of hardware IP using constrained‑random, coverage‑driven methods.
Sunnyvale, CA
11 days ago
Hybrid
debugging
root‑cause
functional tests
constrained-random
verdi
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