Principal Architect – Isolated Gate Driver IC at Larsen & Toubro in Bengaluru, Karnataka, India | Kablio

Role

Description

roadmap strategy

ip reuse

hv layout

isolation standards

system integration

architecture lead

Contribute to long-term roadmap and technology strategy for wide-bandgap driver solutions across all business units
Collaborate with SiC/GaN FET designers, power module architects, and system teams to define drive strength, layout constraints, and thermal performance targets.
Define system-level integration strategy for energy platforms, ensuring reliable performance across wide operating voltages, temperatures, and transient conditions.
Drive IP reuse, design scalability, and enable the gate driver IP to be leveraged across energy, automotive, and industrial portfolios.
Guide the team on HV layout practices, creepage/clearance, EMI reduction, and packaging co-design.
Ensure design meets isolation standards (UL1577, VDE0884, IEC 60747-17) and supports high CMTI (>100 kV/µs) performance.
Lead architecture and design definition for isolated gate driver ICs used with SiC and GaN power switches, optimized for high switching speed, high CMTI, and robustness.
Lead architecture reviews, mentoring, and documentation of system specifications and design decisions.

Requirements

cadence

matlab

sic/gan

uvlo

gate driver

high‑voltage

High/low side output stages (with Miller clamp, active pull-up/down, configurable source/sink)
Diagnostic and telemetry features (SPI/I²C interface, status flags)
Isolation interface (capacitive, magnetic, or optical)
Integrated protections (UVLO, DESAT, SCP, soft turn-off, active clamp)
Isolation technologies and barrier design (capacitive/magnetic/optical)
Tools: Cadence Virtuoso, Spectre, MATLAB, and simulation tools (e.g., PLECS, ADS, LTspice).
Knowledge of high-voltage (>600 V) and high-frequency (>100 kHz–1 MHz) design constraints.
System-level co-design experience with SiC/GaN switches, power modules, and packaged solutions.
Level shifters, push-pull buffers, active clamps, and short-circuit protection
Experience with protection and diagnostics: UVLO, DESAT, OCP, OTP, and integrated fault reporting.
Expert in gate driver circuit design for wide-bandgap devices (SiC MOSFETs, GaN HEMTs).
Architect complete driver solutions including:
High-side/low-side driver pairing and bootstrap techniques

Benefits

Information not given or found

Training + Development

Information not given or found

Interview process

Information not given or found

Visa Sponsorship

Information not given or found

Security clearance

Information not given or found

Company

Overview

Founded in 1946

Year Established

The company was started in 1946 by two Danish engineers.

Revenue Billions USD

Annual Revenue

The company generates tens of billions of USD annually.

A small Bombay firm that evolved into a global powerhouse.
Expanded into major infrastructure and industrial projects worldwide.
Delivers EPC projects in energy, transport, and defense.
Notable projects include power plants, metro rail systems, hydrocarbon facilities, and naval vessels across emerging markets.
Subsidiaries like LTIMindtree and L&T Technology Services drive its footprint in digital engineering and consulting.
Known for tackling large-scale, complex assignments in defense, power, urban transit, and marine engineering.

Culture + Values

Integrity and transparency in all dealings.
Commitment to excellence and innovation.
Customer satisfaction through quality, service, and value.
Respect for the environment and communities.
A culture of teamwork, collaboration, and respect for diversity of thought.
Continuous learning, development, and growth.
Safety as the first priority in all operations.

Environment + Sustainability

Net Zero by 2040

Sustainability Goal

The company aims to achieve net-zero emissions by 2040 through comprehensive sustainability initiatives.

Implementation of energy-efficient technologies in all operations.
Reduction in carbon footprint through sustainable practices.
Investment in renewable energy sources like solar and wind.
Commitment to circular economy principles in product design and waste management.
Promotion of green building initiatives and sustainable infrastructure.

Inclusion & Diversity

Achieving gender balance across all levels of the organization.
Female representation at leadership positions increased year over year.
Commitment to gender-neutral policies and equal pay for equal work.
Fostering an inclusive workplace through mentorship programs and training.

Articles

Careers at L&T

L&T Projects

About L&T

Role

Description

roadmap strategy

ip reuse

hv layout

isolation standards

system integration

architecture lead

Contribute to long-term roadmap and technology strategy for wide-bandgap driver solutions across all business units
Collaborate with SiC/GaN FET designers, power module architects, and system teams to define drive strength, layout constraints, and thermal performance targets.
Define system-level integration strategy for energy platforms, ensuring reliable performance across wide operating voltages, temperatures, and transient conditions.
Drive IP reuse, design scalability, and enable the gate driver IP to be leveraged across energy, automotive, and industrial portfolios.
Guide the team on HV layout practices, creepage/clearance, EMI reduction, and packaging co-design.
Ensure design meets isolation standards (UL1577, VDE0884, IEC 60747-17) and supports high CMTI (>100 kV/µs) performance.
Lead architecture and design definition for isolated gate driver ICs used with SiC and GaN power switches, optimized for high switching speed, high CMTI, and robustness.
Lead architecture reviews, mentoring, and documentation of system specifications and design decisions.

Requirements

cadence

matlab

sic/gan

uvlo

gate driver

high‑voltage

High/low side output stages (with Miller clamp, active pull-up/down, configurable source/sink)
Diagnostic and telemetry features (SPI/I²C interface, status flags)
Isolation interface (capacitive, magnetic, or optical)
Integrated protections (UVLO, DESAT, SCP, soft turn-off, active clamp)
Isolation technologies and barrier design (capacitive/magnetic/optical)
Tools: Cadence Virtuoso, Spectre, MATLAB, and simulation tools (e.g., PLECS, ADS, LTspice).
Knowledge of high-voltage (>600 V) and high-frequency (>100 kHz–1 MHz) design constraints.
System-level co-design experience with SiC/GaN switches, power modules, and packaged solutions.
Level shifters, push-pull buffers, active clamps, and short-circuit protection
Experience with protection and diagnostics: UVLO, DESAT, OCP, OTP, and integrated fault reporting.
Expert in gate driver circuit design for wide-bandgap devices (SiC MOSFETs, GaN HEMTs).
Architect complete driver solutions including:
High-side/low-side driver pairing and bootstrap techniques

Benefits

Information not given or found

Training + Development

Information not given or found

Interview process

Information not given or found

Visa Sponsorship

Information not given or found

Security clearance

Information not given or found