Senior Design Verification Engineer

Description

• Work with ARM cores
• Perform constraint random verification, assertion writing, coverage analysis, debugging.

Requirements

We are seeking an experienced Design Verification Engineer who has at least 8 years of professional work experience with Below skill set:-

Work Experience

• Work on HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows.
• Project experience with ARM based ecosystem components
• Experience with verification tools such as UVM, System Verilog, and Verilog
• Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.
• M7, Coresight, NIC, and other AMBA bus interconnects
• Plus points: experience with DRAM memory controllers and its interfaces
• Understanding of SoC interfaces like QSPI, UART, GPIOs
• Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.
• Strong experience with UVM based verification, setting up co-simulation environments with ARM CPU models
• Capable of working with multiple IP vendors and other IP teams
• Plus points: experience with UCIe
• Familiarity with AMBA bus protocols and SoC system debug infrastructure
• Strong understanding of semiconductor design and verification methodologies

Benefits

Training + Development

Interview process

Visa Sponsorship

Security clearance