Design Verification Engineer

🚀 Work on next-generation SoC/IP/Subsystem verification projects with top global semiconductor clients

• Verify complex interfaces and protocols like PCIe, Ethernet, MIPI, USB, DDR, Wi-Fi, Bluetooth, etc.
• Debug simulation issues and collaborate with design/architecture teams to resolve functional problems.
• Contribute to verification methodology improvement and automation using Perl/Python/C scripting.
• Perform Power-aware verification, Low-power GLS verification, and Mixed-signal verification.
• Define test plans, write and execute test cases, and ensure coverage-driven verification closure.
• Work on ARM Coresight/Cortex-based designs and interconnect verification.
• Develop and implement UVM/SystemVerilog-based verification environments for SoC/IP/Sub-System designs.

(We have multiple positions open across SoC, IP, and Subsystem verification levels.)

⚙️ Exposure to verification methodologies at IP, Subsystem, or SoC levels

✅ Hands-on experience with C, Verilog, and scripting (Python/Perl/Tcl)

🧠 Strong analytical, debug, and problem-solving skills

Experience Range: 4 to 20+ years

If you have experience with protocol-level verification, ARM-based designs, and power-aware or mixed-signal verification, we’d love to connect with you!

✅ Experience in one or more protocols: PCIe / Ethernet / USB / MIPI / DDR / Wi-Fi / Bluetooth

🎓 B.E / B.Tech / M.E / M.Tech in Electronics, ECE, or related disciplines

✅ Low Power & Power-Aware Verification: UPF/CPF, Low-Power GLS

✅ Mixed-Signal Verification: AMS Co-simulation exposure preferred

Technical Skills Required

💡 Exposure to AI, Automotive, 5G, Networking, and IoT domains

✅ ARM Ecosystem: Coresight / Cortex / Subsystem verification

✅ Familiarity with tools such as VCS, Xcelium, Questa, Verdi, DVE, JasperGold

✅ Strong expertise in SystemVerilog & UVM methodology

🌍 Flexible locations: Bangalore | Hyderabad | Pune | Chennai

🤝 Collaborative environment with strong focus on technical excellence & career growth