Senior Design Verification Engineer

Description

• Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

Requirements

• Design Verification Lead- (15+ Years of relevant experience required
• Experience using constrained-random, coverage driven verification or C/C++ verification
• Experience in Electronic Design Automation (EDA) tools and scripting (Python, Tool Command Language (TCL), Perl, Shell) used to build tools and flows for verification environments
• Understanding in at least one of the following areas: computer architecture, Central Processing Unit (CPU), Graphics Processing Unit (GPU), networking, interconnects, fabrics or similar designs
• Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
• Experience with revision control systems like Mercurial (Hg), Git or SVN
• Experience working in a CPU/GPU environment
• Experience in verifying a IP block using standard Design Verification (DV) based techniques
• Senior Design Verification Engineer( 6-14 Years of relevant experience required)

Benefits

We offer flexible work options, including hybrid/Remote arrangements, to support the need of the role and align with company policies. This position is located in Sunnyvale California or Austin Texas

Training + Development

Interview process

Visa Sponsorship

Security clearance