Provides engineering and R&D services across various industries with cutting-edge solutions.
Develop functional tests based on verification test plan
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
Experience in development of UVM based verification environments from scratch
Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies