Senior ASIC Digital Design Engineer

This is an exciting opportunity to work on high-speed digital integrated circuits for a startup who have a groundbreaking technology and have raised over $100million in funding. You will be working on RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the companies next generation products.

• Working with protocols for Optical Communications

• High-Speed Interfaces (Ethernet, SerDes, PCIe etc.)
• B.S. or M.S. in Electrical Engineering, Computer Engineering or similar
• Must have worked with Cadence or Synopsys Electronic Design Automation tools such as Tempus, PrimeTime, Genus, Design Compiler, Formality or JasperGold
• Scripting experience with either Python, TCL or Perl
• A strong background working on Digital ASIC Design with the understanding of complete ASIC design flow from specification to tape-out.
• Experience working with Hardware Description Languages such as Verilog or SystemVerilog
• Experience working on Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain
• Digital Data Communication techniques including scrambling or forward error correction (FEC)

• Full Premium Healthcare